--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   16:48:43 10/23/2013
-- Design Name:   
-- Module Name:   C:/Users/Ling Chun Kai/Documents/NUS modules/CG3207/Lab/CG3207/Test_data_RAM.vhd
-- Project Name:  LAB2
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: DATA_RAM
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY Test_data_RAM IS
END Test_data_RAM;
 
ARCHITECTURE behavior OF Test_data_RAM IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT DATA_RAM
    PORT(
         CLK : IN  std_logic;
         DATA_IN : IN  std_logic_vector(31 downto 0);
         ADDR_IN : IN  std_logic_vector(8 downto 0);
         ENABLE : IN  std_logic;
         WRITE_ENABLE : IN  std_logic;
         DATA_OUT : OUT  std_logic_vector(31 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal DATA_IN : std_logic_vector(31 downto 0) := (others => '0');
   signal ADDR_IN : std_logic_vector(8 downto 0) := (others => '0');
   signal ENABLE : std_logic := '0';
   signal WRITE_ENABLE : std_logic := '0';

 	--Outputs
   signal DATA_OUT : std_logic_vector(31 downto 0);

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: DATA_RAM PORT MAP (
          CLK => CLK,
          DATA_IN => DATA_IN,
          ADDR_IN => ADDR_IN,
          ENABLE => ENABLE,
          WRITE_ENABLE => WRITE_ENABLE,
          DATA_OUT => DATA_OUT
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	


      wait for CLK_period*10;
		
      -- insert stimulus here 

		ENABLE <= '1';
		ADDR_IN <= "000000000";
		
		wait for CLK_PERIOD;
		
		ADDR_IN <= "000000001";
		
		wait for CLK_PERIOD;
		
		ADDR_IN <= "000000010";

      wait for CLK_PERIOD;
		
		WRITE_ENABLE <= '1';
		ADDR_IN <= "111110000";
		DATA_IN <= x"0ABCDEFA";
		
		wait for CLK_PERIOD;
		
		WRITE_ENABLE <= '0';
		ADDR_IN <= "111101111";
		
		wait for CLK_PERIOD;
		
		ADDR_IN <= "111110000";
		
		wait;
		
   end process;

END;
